Stacked CMOS image sensors are said to combine superior image quality and advanced functionality with compact size. In contrast to conventional back-illuminated CMOS image sensors, which require a supporting substrate that carries the pixel section, the back-illuminated pixel section of stacked CMOS sensors is layered onto chips containing the circuit for signal processing. Sony said demand for these image sensors is anticipated to further increase, particularly due to the strong demand for mobile devices such as smartphones and tablets.
The investment is primarily intended to reinforce Nagasaki TEC’s layering process production capabilities, as well as Kumamoto TEC’s mastering process facilities. On January 29, 2014, Sony had announced to establish in the Yamagata Technology Center as a facility mainly conducting the mastering process. The current investment is expected to enable Sony to complete subsequent stages of production, including the layering process, at Nagasaki TEC on semiconductor chips that have undergone the mastering process at Yamagata TEC, providing the company with a fully integrated production system for stacked CMOS image sensors.
Sony’s mid- to long-term plan includes an increase of its total production capacity for image sensors to approximately 75,000 wafers per month. By August 2015, the capacity is to expected to approximately 68,000 wafers per month, compared with approximately 60,000 wafers per month today.
The total investment will be approximately 35 billion yen (US$ 344 million/Euro 256 million).